1. Field of the Invention
The invention relates generally to semiconductor substrate manufacturing, and more particularly to a method of forming an ultra-thin and uniform layer of Si atop an isolation region.
2. Background of the Invention
In semiconductor processing, silicon-on-insulator (SOI) technology is becoming increasingly important since it permits the formation of high-speed integrated circuits. In SOI technology, a buried insulating layer electrically isolates a top Si-containing layer from a bottom Si-containing layer. The top Si-containing layer, which is oftentimes referred to in the art as the SOI layer, is generally the area in which active devices such as transistors are formed. Devices formed using SOI technology offer many advantages over their bulk Si counterparts including, for example, higher performance, absence of latch-up, higher packing density and low voltage applications.
In the semiconductor industry, the SOI thickness has been scaled down in every SOI device technology generation. Current technology trends are for providing SOI devices that have thin Si channels. Thin Si channel devices, which are formed in the top Si-containing layer of an SOI substrate, have demonstrated excellent scalability.
Previously, thin Si-containing layers have been formed using conventional layer transfer or oxygen ion implantation. Oxygen implantation creates high internal stresses, which can disadvantageously result in dislocation formation that reduces device performance. Oxygen implantation also disadvantageously requires a very high temperature anneal, wherein the annealing temperature may be on the order of 1100° C. or higher. Si-containing layer formation via layer transfer cannot be selectively applied to specific regions, since layer transfer disadvantageously affects the entire surface of the substrate. Therefore, prior layer transfer methods cannot be easily integrated into forming substrates that simultaneously comprise SOI and bulk-Si portions.
Prior processing methods for forming thin layers of Si have difficulties forming a uniform and ultra-thin layer of Si on an isolation region. The term “uniform” is meant to denote that the thickness of the ultra-thin Si layer is substantially constant and continuous. The term “ultra-thin” is used throughout this application to denote a Si-containing layer having a vertical thickness that is thin enough to be fully depleted when a field effect transistor is formed on top of the Si-containing layer. The term “fully depleted” denotes that the Si-containing layer is fully depleted of mobile charge carriers when an off voltage is applied to the gate region of a field effect transistor (FET), which is positioned on the Si-containing layer.
In view of the state of the art mentioned above, there is a continued need for providing a method of forming a uniform and ultra-thin layer of Si atop an insulating region, wherein the ultra-thin Si layer has a thickness that fully depletes when employed as the channel of a FET device.